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74ACT174
HEX D-TYPE FLIP FLOP WITH CLEAR
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HIGH SPEED: fMAX = 200MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74ACT174B 74ACT174M T&R 74ACT174MTR 74ACT174TTR
DESCRIPTION The 74ACT174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the clock pulse.
When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
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74ACT174
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 8 16 SYMBOL CLEAR Q0 to Q5 D0 to D5 CLOCK GND VCC NAME AND FUNCTION Asynchronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH, Edge Trigger) Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS CLEAR L H H H
X : Don't Care
OUTPUT FUNCTION CLOCK X Q L L H Qn NO CHANGE CLEAR
D X L H X
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
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74ACT174
ABSOLUTE MAXIMUM RATINGS
Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 300 -65 to +150 300 Unit V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -55 to 125 8 Unit V V V C ns/V
1) VIN from 0.8V to 2.0V
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74ACT174
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Low Level Output Voltage 4.5 5.5 4.5 5.5 II ICCT ICC IOLD IOHD Input Leakage Current Max ICC/Input Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 A IO=-50 A IO =-24 mA IO =-24 mA IO=50 A IO=50 A IO =24 mA IO =24 mA VI = VCC or GND VI = VCC - 2.1V VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 0.6 4 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 TA = 25C Min. 2.0 2.0 Typ. 1.5 1.5 1.5 1.5 4.49 5.49 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1 1.5 40 75 -75 Max. Value -40 to 85C Min. 2.0 2.0 0.8 0.8 4.4 5.4 3.7 4.7 0.1 0.1 0.5 0.5 1 1.6 80 50 -50 A mA A mA mA V Max. -55 to 125C Min. 2.0 2.0 0.8 0.8 V V Max. Unit
VIH V IL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 5.0 (*) 5.0 (*) 5.0 (*) 5.0 (*) 5.0 (*) TA = 25C Min. 1.5 1.5 Typ. 6.0 7.0 3.0 3.0 0.5 Max. 10.5 9.5 4.5 4.5 1.5 Value -40 to 85C Min. Max. 11.5 11.0 5.0 5.0 1.5 -55 to 125C Min. Max. 11.5 11.0 5.0 5.0 1.5 ns ns ns ns ns Unit
tPLH tPHL Propagation Delay Time CLOCK to Y tPLH tPHL Propagation Delay Time CLEAR to Y tWL CLEAR Pulse Width, LOW tW CLOCK Pulse Width ts Setup Time D to CLOCK, HIGH or LOW th Hold Time D to CLOCK, HIGH or LOW tREM Recovery Time CLEAR to CLOCK fMAX Maximum CLOCK Frequency
(*) Voltage range is 5.0V 0.5V
5.0 (*) 5.0 (*) 5.0 (*) 165
1.0 0.0 200
2.0 0.5 140
2.0 0.5 140
2.0 0.5
ns ns MHz
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74ACT174
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 fIN = 10MHz TA = 25C Min. Typ. 4 35 Max. Value -40 to 85C Min. Max. -55 to 125C Min. Max. pF pF Unit
CIN C PD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT
C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500 or equivalent R T = ZOUT of pulse generator (typically 50)
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74ACT174
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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74ACT174
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
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74ACT174
Plastic DIP-16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
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74ACT174
SO-16 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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74ACT174
TSSOP16 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 4.9 6.25 4.3 5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.20 5.1 6.5 4.48 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
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74ACT174
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom (c) http://w ww.st.com
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